This invention relates to a voltage comparator, and more particularly to a voltage comparator using CMOS transistors.
A conventional CMOS voltage comparator comprises, as shown, for example, FIG. 1, a differential amplifier 11 including N channel differential transistors Q1 and Q2, N channel constant current transistor Q3, P channel load transistors Q4 and Q5 and a CMOS inverter 12 formed of CMOS transistors Q6 and Q7. A reference voltage V.sub.R is applied to the gate of transistor Q1 and an input voltage V.sub.I to be compared with the reference voltage V.sub.R is applied to the gate of transistor Q2.
In operation of the voltage comparator, when the input voltage V.sub.I is higher than the reference voltage V.sub.R, the drain voltage of transistor Q2, that is, an output voltage of differential amplifier 11 is at a logic level "0" (ground), causing an output voltage V.sub.OUT of the CMOS inverter 12 to go to a logic level "1" (V.sub.DD). Conversely when the input voltage V.sub.I is lower than the reference voltage V.sub.R, the drain voltage of transistor Q1 is at logic level "0", rendering transistor Q5 conducting. Therefore, the output voltage of the differential amplifier 11 is at logic level "1", and the output voltage V.sub.OUT of inverter 12 is at logic level "0".
With differential amplifier 11 acting as an analog circuit, current flows from a power supply terminal V.sub.DD to a ground power supply terminal, resulting in an increase in power dissipation.
The above-mentioned voltage comparator is integrated on a semiconductor substrate. When threshold voltages of transistors used vary from chip to chip, it is difficult to assure a desired property of the differential amplifier. To suppress variations in the threshold voltages of transistors which occur from chip to chip, it is necessary to precisely design elements used and rigidly control the manufacturing processes of an integrated circuit. When the above-mentioned voltage comparator is large-scale integrated with other circuits, it is necessary to enlarge the dimension of transistors, that is, an area occupied by the differential amplifier 11 in order to restrict variations in the threshold voltages of transistors used within an allowable range.